1. Field of the Invention
The invention relates to an electronic device and a method for fabricating the same, and particularly relates to a semiconductor device and a method for fabricating the same.
2. Description of Related Art
As science and technology advance, it has become a trend to integrate devices in the memory cell array region and the peripheral circuit region in the same chip to reduce the cost, simplify the process, and reduce the chip area. However, there is a significant step height in the boundary region between the memory cell array region and the peripheral circuit region, making subsequent processes more complex.
FIG. 1 is a cross-sectional schematic view illustrating a conventional semiconductor device. Referring to FIG. 1, for example, to reduce a height of a stack layer 12 on a surface of a substrate 10 in a conventional semiconductor device, a part of the substrate 10 in a memory cell array region 110 is removed for embedding the stack layer 12 therein. However, such method results in a significant step height in a boundary region 130 between the memory cell array region 110 and a peripheral circuit region 120. To solve the issue of step height, a relatively long distance (approximately 3 μm) needs to be kept as the boundary region 130 between the memory cell array region 110 and the peripheral circuit region 120. Then, after a series of complicated processes, such as photolithography, etching, film deposition, and planarization (e.g. chemical mechanical polishing, CMP) processes, etc., a huge and deep trench 18 is formed in the boundary region 130. Meanwhile, during the processes, a silicon nitride layer 14 and a silicon oxide layer 16 are filled in the trench 18. However, since the silicon nitride layer 14 and the silicon oxide layer 16 have different etching rates, after removing redundant parts of the silicon nitride layer 14 and the silicon oxide layer 16 by using a wet etching process, recesses 20 are commonly produced at two sides of the silicon nitride layer 14, and a top surface of the silicon oxide layer 16 is slightly higher than top surfaces of the memory cell array region 110 and the peripheral circuit region 120. As the planarization process at the boundary requires complicated steps in the manufacturing process, the cost thereof is high. Besides, the remaining height difference according to the conventional method also increases the complexity of subsequent processes, making product reliability reduced.
Thus, how to simplify the process for treating the boundary region between the memory cell array region and the peripheral circuit region and minimize the difference in step height between regions, thereby reducing the complexity of the subsequent processes, increasing the chip area, and reducing the cost at the same time has become an important issue.